1. Field of the Invention
The invention relates generally to the field of conductor interconnections within microelectronics fabrications. More particularly, the invention relates to the field of dual damascene metal interconnection layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ conductor lines to interconnect the electrical devices from which they are made. As device dimensions have become smaller, the requirements placed on interconnections have become more stringent. The number and complexity of the interconnections require multiple levels of wiring to interconnect the various devices, so that there has developed a need for multi-level interconnection wiring for microelectronics fabrications with increasing demands and constraints on materials and methods.
In order to decrease electrical resistance as dimensions and conductor cross-sections have shrunk, the art of microelectronics fabrication has resorted to conductors having the highest electrical conductivity available. In addition, there has been sought the reduction of resistance due to via contacts required between multiple levels of interconnection wiring. Finally, the need form more levels of interconnection wiring necessitates fabrication methods which maintain surface planarity as the number of layers required to be formed one on top of another has increased. The formation of interconnection lines by subtractive etching of a pattern in a conductor layer leaves raised pattern profiles which are often difficult to planarize with subsequently deposited dielectric layers, so that methods placing conductor lines within dielectric layer surfaces are under consideration.
Methods and materials providing high density interconnections with low electrical resistance have been developed which are generally satisfactory for meeting the stringent requirements of microelectronics fabrication. These include forming the interconnection patterns from copper metal because of its intrinsically high electrical conductivity. In addition, methods have been developed to form the interconnection lines inlaid within depressions or trenches formed within dielectric layers employing the method know as "damascene" for form a particular interconnection wiring level whose conductor layer surface is then approximately co-planar with the surface of the dielectric layer. When the inlaid conductor interconnection line and its associated via contact to another wiring level are formed in one integral structure, the method is known as a "dual damascene" stacked conductor interconnection layer. Such integral stacked conductor layers have reduced contact resistance. This method of dual damascene electrical interconnections is not without problems, however.
For example, the dual damascene method conventionally employs within the IMD layer upper and lower silicon containing dielectric layers separated by an intermediate dielectric layer of a different material which functions as an etch stop layer when forming an inlaid pattern by selective etching of the upper dielectric layer. When the upper and lower inter-level metal dielectric (IMD) layers are formed of silicon oxide dielectric material, the intermediate layer is commonly formed from a silicon nitride dielectric material as an inherently thin layer with a high dielectric constant. This may result in increased inter-level capacitance as well as fabrication and yield difficulties. In particular, the silicon nitride layer may not be sufficiently resistant towards the etching agent of the upper dielectric layer when formed of silicon oxide dielectric material during etching of the wiring trench pattern.
It is therefore towards the goal of forming within a microelectronics fabrication an inter-level metal dielectric (IMD) layer with improved dual damascene capability that the present invention is generally directed.
Various methods have been disclosed for forming damascene interconnection wiring inlaid within dielectric layers within microelectronics fabrication wherein there are multi-level interconnection levels and inter-level capacitance concerns.
For example, Fiordalice et al., U.S. Pat. No. 5,578,523, disclose a method for forming inlaid conductor layers with reduced dishing of the conductor layer surface during chemical mechanical polish planarization. The method employs a polishing assist layer formed of aluminum nitride over the conductor layer formed of aluminum, whereby the polishing rates of both materials are similar.
Further, Huang et al., in U.S. Pat. No. 5,635,423, disclose a dual damascene method enhanced trench/via profile. The method forms a via hole pattern in an upper inter-level metal dielectric (IMD) layer by a first etch method, followed by a trench pattern in the upper IMD layer and a via hole pattern in a lower IMD layer by a second etch method. Upper and lower IMD layers are formed of silicon oxide dielectric material, and the intermediate etch stop layer is formed of a silicon containing dielectric material or polysilicon material.
Further still, Chiang et al., in U.S. Pat. No. 5,739,579 and U.S. Pat No. 5,817,572, disclose methods for forming inlaid patterned conductors in contact with inlaid conductive vias formed through dielectric layers separated by an etch stop layer wherein there is improved process control. The dielectric layers are silicon oxide dielectric layers and the etch stop layer may be a silicon nitride dielectric layer. The method employs multiple application of the single damascene technique.
Still yet further, You et al., in U.S. Pat. No. 5,760,480, disclose a method for forming a low resistance-capacitance (RC) delay interconnection pattern without a barrier layer. The method employs copper metal interconnections and a bonding layer formed of low dielectric constant dielectric material which also serves as a barrier layer to obtain low electrical resistance R and low capacitance C.
Finally, Lee et al., in U.S. Pat. No. 5,767,582, disclose a method for forming interconnection conductor lines separated by less than one micron without electrical short circuits. The method employs a damascene process to form inlaid conductor lines after treating the insulator matrix layer with ammonium hydroxide and hydrogen peroxide to attenuate sensitivity to shorting.
Desirable in the art of microelectronics fabrication are additional methods for forming improved damascene interconnection patterns of inlaid conductive material.
It is towards these goals that the present invention is generally and specifically directed.